verilog 仿真时读取txt文件

1reg [7:0]data; 
2initial begin
3     #10 clk =0;
4    forever #4 clk = ~clk;
5 end
6 initial begin
7     #20 rst=1;
8     #20 rst=0;
9 end
10reg [7:0]data_sin[160000:0];  ////改动点数据矩阵长度设置
11integer i;
12    initial  
13        begin  
14            i=0;
15            begin  
16            $readmemb("D:/Chapter_8/E8_1_QAMModem/QAM.txt",data_sin,0,160000); ///改动点数据矩阵长度  注意是“/”  而不是“\”
17            end  
18            forever
19            begin
20                @(posedge clk)
21                    begin
22                        i <= i+1;
23                        din <= data_sin[i];
24                    end
25            end
26        end 
27endmodule

matlab 写txt文本的代码

1fid = fopen('data.txt','w');
2for oo=1:1:i
3if mod(oo,10) == 0
4fprintf(fid,'%f,%f,\n',sI1(oo),sQ1(oo));
5else
6fprintf(fid,'%f,%f,',sI1(oo),sQ1(oo));
7end
8end
9fclose(fid);

verilog 对应的写文件，写入IQ数据

1integer file_out;
2initial
3begin
4    file_out = $fopen("mI.txt");
5    if (!file_out) begin
6        $finish;
7    end
8end            
9
10wire signed [23:0] dout_s = fifo_fft_data[47:24];
11
12always @ (posedge clk) 
13begin  
14    if(fifo_fft_valid)
15    $fdisplay(file_out, "%d", dout_s);
16end
17
18integer file_out_Q;
19initial
20begin
21    file_out_Q = $fopen("mQ.txt");
22    if (!file_out_Q) begin
23        $finish;
24    end
25end            
26
27wire signed [23:0] dout_s_Q = fifo_fft_data[23:0];
28
29always @ (posedge clk) 
30begin  
31    if(fifo_fft_valid)
32    $fdisplay(file_out_Q, "%d", dout_s_Q);
33end
34
35对应以上文件的matlab 读取数据：
36
37%读取FPGA仿真出的数据
38clc;
39clear;close all;
40
41fid=fopen('mI.txt','r');
42[di,N]=fscanf(fid,'%lg',inf);
43fclose(fid);
44fid=fopen('mQ.txt','r');
45[dq,N]=fscanf(fid,'%lg',inf);
46fclose(fid);
47exp1=di+dq*1i;
48% exp2 = exp1(25000:30000);
49% exp2 = exp1(1024:8192);
50exp2 = exp1;
51plot(di);
52figure;
53plot(dq);
54figure;
55plot(20*log10(abs(fft((exp2).* window(@gausswin,length(exp2),4)))));